FPGA Development

• Design, simulation, verification, implementation, Altera and Xilinx
• Hardware based Computing, Signal Processing, DDS implementation
• MATLAB models to HDL translation, optimization and implementation
• Extensive proven IP libraries for interfacing ADCs, DACs, sensors and buses
• Power, signal integrity and PCB layout optimization

Interfaces:

• SPI, I2C, PCI, PCI-e, AquadB, High Speed Ser/Des, ADC, DAC, Ethernet, safety logic and others

FPGA Families:

• Altera: Cyclone, MAX, Stratix
• Xilinx: Virtex, Zynq
• Recent Targets: Zed Board, Micro Zed

We are using following tools and languages:

• Quartus, Modelsim, SignalTap. TimeQuest
• PlanAhead, XST, ISE, ChipScope, ISim, Vivado, Vivado HLS
• Verilog, VHDL, AHDL, System C, C/C++, MATLAB, scripting

 
 
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